Modules Section

This is a local mirror of the Altera FreeCore Library. It is no longer supported.

Altera Module Library

Note:

This section contains functions written in AHDL - the Altera proprietary HDL language.

The source files for functions #1 to #16 can be found at the download page. Follow the link at the bottom of this page.

Functions #17 to #28 are provided as .zip files with included documentation (if provided).

Contributed by: Module Description

#1:
Rune Baeverrud Divide By N Frequency Divider
This cascadeable function divides a frequency by any integer number and is used for timing generation in other modules, e.g. the Compact UART Reference Design or the I2C Controller Reference Design.

#2:
Rune Baeverrud Compact UART, Transmitter Module
The Compact UART transmitter provides a fully functional asynchronous serial transmitter. Interfacing to logic or a microprocessor is easily accomplished using the control and status signals provided.

#3:
Rune Baeverrud Compact UART, Receiver Module
The Compact UART receiver provides a fully functional asynchronous serial receiver. Interfacing to logic or a microprocessor is easily accomplished using the control and status signals provided.

#4:
Rune Baeverrud Compact UART Reference Design
A complete UART with microprocessor interface. Just drop it in and off you go.

#5:
Rune Baeverrud I2C Controller
This is an I2C Controller which may be used as a controller in single master systems. Interfacing to logic or a microprocessor is easily accomplished using the control and status signals provided.

#6:
Rune Baeverrud I2C Controller Reference Design
A complete I2C Controller with microprocessor interface. Just drop it in and off you go.

#7:
Woody Johnson Gray Code Counter
The gray module implements a parameterized width gray code sequence counter. Gray code count sequences are distinguished by the fact that only one bit changes as the counter goes through it's sequence.

#8:
Rune Baeverrud 512-point Cosine
This is a 512 points (128 points / quadrant) cosine function using a single 256 point lookup-table (one EAB). 7 bits + sign bipolar or 8 bit unipolar output resolution, giving a Signal-to-Noise Ratio (SNR) of more than 50dB.

#9:
Rune Baeverrud 512-point Sine
This is a 512 points (128 points / quadrant) sine function using a single 256 point lookup-table (one EAB). 7 bits + sign bipolar or 8 bit unipolar output resolution, giving a Signal-to-Noise Ratio (SNR) of more than 50dB.

#10:
Rune Baeverrud Numerically Controlled Oscillator/Modulator
This is a very high speed Numerically Controlled Oscillator/Modulator achieving an operating speed of more than 80MHz input clock frequency using an Altera FLEX 10K -3 device.

#11:
Rune Baeverrud VGA Sync Generator
This module makes it very easy to generate the signals required for output to an industry standard VGA computer screen. A number of status output signals are provided for easy synchronizing to external pixel data.

#12:
Woody Johnson MII Management Interface Controller
This is a design that can be used to read or write a register value as defined by the IEEE 802.3 MII Management Interface.

#13:
Iain
Rankin Corner Bender
This LPM function was developed to permit the most efficient separation of the component bitplanes in an image for display on a fast binary array modulator, using pulse width modulation

#14:
Frank
Rodler Dynamic RAM Controller
Dynamic RAMs are still the cheapest way to implement memory for microprocessor systems. If there is a CPLD already planed in the new design, the DRAM controller can be easily added to the device.

#15:
Woody
Johnson Linear Feedback Shift Register (LFSR)
This is a design that can be used to implement a linear feedback shift register (LFSR) of various lengths. Such registers are useful for replacing counters when the count sequence is unimportant (such as in implementing fifo head and tail pointers) or were only the terminal count value is used.

#16:
Rune Baeverrud Variable Frequency Divider
This function is similar to the div_by_n function also found in the FreeCore Library. The difference is that while div_by_n divides a frequency by a fixed value provided as a parameter, var_div will divide a frequency by a variable value provided at it's D[] input

#17:
Steven Groom Percentage Module, outputs A*100/B

#18:
Steven Groom Improved UART

#19:
Keith Willis (NetSoft) Fully Programmable UART, version 2.1

  - Master clock frequency(FCLK) is entered as a module parameter.
  - Maximum master clock frequency=50MHz for -2 grade parts.
  - Maximum Bit Rate=12.5MBits/s at FCLK=50MHz for -2 grade parts.
  - The UART may be used as an embedded module according to the "EMBEDDED" module parameter.
  - UART has separate Input & Output Data Buses for use as an embedded module in a larger design.
  - Digital Filter Depth (FILTER_DEPTH) is entered as a module parameter.
  - A FIFO is integrated into the Receiver if the USE_RxFIFO module parameter = "YES".
  - A FIFO is integrated into the Transmitter if the USE_TxFIFO module parameter = "YES".
  - The depth of the Rx FIFO is determined by the RxFIFO_DEPTH module parameter.
  - The depth of the Tx FIFO is determined by the TxFIFO_DEPTH module parameter.
  - The FIFO will be automatically implemented in an EAB if the device family supports this feature.
  - If the FIFO is implemented in an EAB UART Read and Write timing should be as shown below.
  - The FIFO will not allow data underflow or overflow.
  - Number of logic cells used approximately 338, (without FIFO's).
  - Number of logic cells used approximately 446, (RxFIFO_DEPTH=TxFIFO_DEPTH=32, USE_EAB="YES").
  - All UART asynchronous inputs, (/CTS, /DSR, Rx) are digitally filtered by a 3-stage filter.
  - 5/6/7/8 Data Bits, 1/1.5/2 Stop Bits, N/O/E Parity.
  - Standard CPU interface.
  - UART supports up to 6 maskable interrupts and 6 status flags.
  - A common interrupt line for all interrupt events.
  - 10 Standard Baud rates, from 1200 to 115200.
  - 127 User Baud rates, from FCLK/4 to FCLK/256.
  - Handshaking may be controlled internally by the UART or externally via the CPU.
  - The UART handshaking signals, (/RTS, /CTS, /DTR, /DSR) are active low.
  - 4 Error flags for Invalid Start Bit, Framing Error, Parity Error, & OverRun Error.
  - Transmitter enabled by new Data Write to TxReg.
  - New data may be written to the TxReg during transmission.
  - Status Register Rx bits cleared on Rx Data Register Read, (see Status Register notes).
  - Status Register Tx bits cleared on Tx Data Register Write, (see Status Register notes).
  - Receiver and Transmitter Reset by Configuration Register or Baud-Rate Register Write.
  - Receiver synchronizes off the start bit.
  - Receiver samples all incoming bits at the center of each bit.

#20:
Nik Snoek PRBS module

#21:
Peter Szymansky Byte Wide CRC32 Generator/Detector

#22:
Steven Groom Bit Serial Multiplier

#23:
Steven Groom Arithmetic Logic Unit

#24:
Steven Groom Sine/Cosine using the CORDIC algorithm

#25:
Sven Zeisberg Generating Sine/Cosine using integrators

#26:
Steven Groom Sequential multiplier using Booth's Algorithm

#27:
Steven Groom Very fast exp(i), Sine/Cosine

#28:
pealed@
phasemetrics.com Parameterized variable length pipeline

Go to the FreeCore Library DOWNLOAD page!

Last updated 08 Feb 2001 12:38

Contributed by:	Module Description
#1: Rune Baeverrud	Divide By N Frequency Divider This cascadeable function divides a frequency by any integer number and is used for timing generation in other modules, e.g. the Compact UART Reference Design or the I2C Controller Reference Design.
#2: Rune Baeverrud	Compact UART, Transmitter Module The Compact UART transmitter provides a fully functional asynchronous serial transmitter. Interfacing to logic or a microprocessor is easily accomplished using the control and status signals provided.
#3: Rune Baeverrud	Compact UART, Receiver Module The Compact UART receiver provides a fully functional asynchronous serial receiver. Interfacing to logic or a microprocessor is easily accomplished using the control and status signals provided.
#4: Rune Baeverrud	Compact UART Reference Design A complete UART with microprocessor interface. Just drop it in and off you go.
#5: Rune Baeverrud	I2C Controller This is an I2C Controller which may be used as a controller in single master systems. Interfacing to logic or a microprocessor is easily accomplished using the control and status signals provided.
#6: Rune Baeverrud	I2C Controller Reference Design A complete I2C Controller with microprocessor interface. Just drop it in and off you go.
#7: Woody Johnson	Gray Code Counter The *gray* module implements a parameterized width gray code sequence counter. Gray code count sequences are distinguished by the fact that only one bit changes as the counter goes through it's sequence.
#8: Rune Baeverrud	512-point Cosine This is a 512 points (128 points / quadrant) cosine function using a single 256 point lookup-table (one EAB). 7 bits + sign bipolar or 8 bit unipolar output resolution, giving a Signal-to-Noise Ratio (SNR) of more than 50dB.
#9: Rune Baeverrud	512-point Sine This is a 512 points (128 points / quadrant) sine function using a single 256 point lookup-table (one EAB). 7 bits + sign bipolar or 8 bit unipolar output resolution, giving a Signal-to-Noise Ratio (SNR) of more than 50dB.
#10: Rune Baeverrud	Numerically Controlled Oscillator/Modulator This is a very high speed Numerically Controlled Oscillator/Modulator achieving an operating speed of more than 80MHz input clock frequency using an Altera FLEX 10K -3 device.
#11: Rune Baeverrud	VGA Sync Generator This module makes it very easy to generate the signals required for output to an industry standard VGA computer screen. A number of status output signals are provided for easy synchronizing to external pixel data.
#12: Woody Johnson	MII Management Interface Controller This is a design that can be used to read or write a register value as defined by the IEEE 802.3 MII Management Interface.
#13: Iain Rankin	Corner Bender This LPM function was developed to permit the most efficient separation of the component bitplanes in an image for display on a fast binary array modulator, using pulse width modulation
#14: Frank Rodler	Dynamic RAM Controller Dynamic RAMs are still the cheapest way to implement memory for microprocessor systems. If there is a CPLD already planed in the new design, the DRAM controller can be easily added to the device.
#15: Woody Johnson	Linear Feedback Shift Register (LFSR) This is a design that can be used to implement a linear feedback shift register (LFSR) of various lengths. Such registers are useful for replacing counters when the count sequence is unimportant (such as in implementing fifo head and tail pointers) or were only the terminal count value is used.
#16: Rune Baeverrud	Variable Frequency Divider This function is similar to the div_by_n function also found in the FreeCore Library. The difference is that while div_by_n divides a frequency by a fixed value provided as a parameter, var_div will divide a frequency by a variable value provided at it's D[] input
#17: Steven Groom	**Percentage Module, outputs A100/B***
#18: Steven Groom	*Improved UART*
#19: Keith Willis (NetSoft)	*Fully Programmable UART, version 2.1* - Master clock frequency(FCLK) is entered as a module parameter. - Maximum master clock frequency=50MHz for -2 grade parts. - Maximum Bit Rate=12.5MBits/s at FCLK=50MHz for -2 grade parts. - The UART may be used as an embedded module according to the "EMBEDDED" module parameter. - UART has separate Input & Output Data Buses for use as an embedded module in a larger design. - Digital Filter Depth (FILTER_DEPTH) is entered as a module parameter. - A FIFO is integrated into the Receiver if the USE_RxFIFO module parameter = "YES". - A FIFO is integrated into the Transmitter if the USE_TxFIFO module parameter = "YES". - The depth of the Rx FIFO is determined by the RxFIFO_DEPTH module parameter. - The depth of the Tx FIFO is determined by the TxFIFO_DEPTH module parameter. - The FIFO will be automatically implemented in an EAB if the device family supports this feature. - If the FIFO is implemented in an EAB UART Read and Write timing should be as shown below. - The FIFO will not allow data underflow or overflow. - Number of logic cells used approximately 338, (without FIFO's). - Number of logic cells used approximately 446, (RxFIFO_DEPTH=TxFIFO_DEPTH=32, USE_EAB="YES"). - All UART asynchronous inputs, (/CTS, /DSR, Rx) are digitally filtered by a 3-stage filter. - 5/6/7/8 Data Bits, 1/1.5/2 Stop Bits, N/O/E Parity. - Standard CPU interface. - UART supports up to 6 maskable interrupts and 6 status flags. - A common interrupt line for all interrupt events. - 10 Standard Baud rates, from 1200 to 115200. - 127 User Baud rates, from FCLK/4 to FCLK/256. - Handshaking may be controlled internally by the UART or externally via the CPU. - The UART handshaking signals, (/RTS, /CTS, /DTR, /DSR) are active low. - 4 Error flags for Invalid Start Bit, Framing Error, Parity Error, & OverRun Error. - Transmitter enabled by new Data Write to TxReg. - New data may be written to the TxReg during transmission. - Status Register Rx bits cleared on Rx Data Register Read, (see Status Register notes). - Status Register Tx bits cleared on Tx Data Register Write, (see Status Register notes). - Receiver and Transmitter Reset by Configuration Register or Baud-Rate Register Write. - Receiver synchronizes off the start bit. - Receiver samples all incoming bits at the center of each bit.
#20: Nik Snoek	*PRBS module*
#21: Peter Szymansky	*Byte Wide CRC32 Generator/Detector*
#22: Steven Groom	*Bit Serial Multiplier*
#23: Steven Groom	*Arithmetic Logic Unit*
#24: Steven Groom	*Sine/Cosine using the CORDIC algorithm*
#25: Sven Zeisberg	*Generating Sine/Cosine using integrators*
#26: Steven Groom	*Sequential multiplier using Booth's Algorithm*
#27: Steven Groom	*Very fast exp(i), Sine/Cosine*
#28: pealed@ phasemetrics.com	*Parameterized variable length pipeline*